Fastest signal delivery on CMOS intergrated circuit.

This study was performed in exporatory memory department to achieve fastest CMOS memory design in a confined process technology for a given load condition.

The final goal is to find number of stages and the size of each of the stage. This work was not published in any research journal. During the study of this subject I found new concept about Epsilon Plane is exist and any optimal condition may located on this plane if the structure is symetric.