The rapid proliferation of connectivity, availability of cloud computing, and miniaturization of sensors and communications chips have made it possible for many devices to be networked together to create the Internet of things (IoT). Although the number of deployments is still relatively small, organizations worldwide are pushing ahead with deployment and the demand for a low-power sensor that is flexible (i.e. wearable) and intelligent (i.e. ability to differentiate on its own of what’s being detected) is set to rise with this deployment. Nevertheless, until we have solved the problems of high power consumption (i.e. in mW range) in MOS sensor or the short shelf life of electrochemical sensors, conventional gas sensors as described above cannot be efficiently integrated into a wireless sensor network. (e.g. Imagine the heavy maintenance workload of having to replace millions and millions of electrochemical sensors in an IoT network every year or the power consumption from a billion devices consuming milli-Watt of electrical power). Therefore, we need a low power (preferably in nano-watt range) sensor with a long shelf life (> 5 years) and artificial sensing intelligence for universal sensing. Sensors with these qualities can then be more efficiently integrated into an IoT network. Specifically, the goal is to achieve: i. Accuracy: low noise and reliable data ii. Useful Insight: Non-invasive sensing with multiple parameters iii. Packaging: Low cost and small size, almost invisible iv. Ultra-low power: reliable measurement

Develop method to extract optical properties of amorphous semiconductor thin film. Single and multiple layer, Uniform and non-uniform thickness.

This project demonstrated the viability of fabricating As2S3 waveguides with magnetron sputtering and also the feasibility of integrating them on LiNbO3 substrate with on-chip optical amplification.

Miniaturization of complementary metal-oxide-semiconductor (CMOS) field-effect transistors (FETs) has led to extraordinary improvements in the computational speeds, functionality and cost of microprocessors. Today, the physical gate length of transistor is fast approaching its downscaling limit, where all CMOS FETs, irrespective of their channel material, will start experiencing unacceptable level of thermally induced errors around 5nm gate lengths at room temperatures. When coupled with high demand for higher performance and lower power consumption in electronic systems, the microelectronics industry urgently needs new innovation in materials and transistor architectures to extend device performance and scalability into sub-5nm regime and beyond. This research proposal aims to address key challenges associated with the making of nanoelectronics and optoelectronics based on two-dimensional (2D) materials, which could potentially be the next-generation transistor technologies beyond CMOS.